IP Solutions: Partners and Supported Libraries
Click below to view technology specific libraries.
0.13μm: TS13SL — Mixed Signal CMOS
Analog IPs: MOSCAD (NEW), Ramon Chips and Synopsys
I/O Libraries: Aragio Solutions, ARM, Ramon Chips and Synopsys
Memory Compilers: ARM, Ramon Chips and Synopsys
NVMs: Kilopass and Novocell
Standard Cell Libraries: ARM, Ramon Chips and Synopsys
Analog IPs (0.13μm: TS13SL — Mixed Signal CMOS)
| Library | Partner |
| LVDS Reference | |
| LVDS Receiver | |
| LVDS Transmitter | |
| NEW High Precision Silicon Oscillator | |
| Rad-hard All-digital DLL library | |
| Rad-hard Embedded capless voltage regulator, from 2.5V to 1.2V | |
| PLL 25-250MHz | |
| PLL 56.25-500MHz | |
| USB2.0 OTG UTMI + Level 3 PHY |
I/O Libraries (0.13μm: TS13SL — Mixed Signal CMOS)
| Library | Partner |
| ESD I/O Interface for High-speed USB OTG | |
| SSTL2 Class I PL 3.3V 210MHz | |
| SSTL2 Class II PL 3.3V 250MHz | |
| LVDS SE PL 3.3V 850MHz | |
| NGPIO PL 3.3V | |
| USB1.1 In-Line I/O Library | |
| GPIO Inline Pad Library 3.3v | |
| GPIO Staggered Pad Library 3.3v | |
| HSTL Class I PL 3.3V 1.5V 266MHz | |
| HSTL Class II PL 3.3V 1.5V 266MHz | |
| Rad-hard DDR2 I/O library | |
| Rad-hard I/O cell library | |
| Rad-hard LVDS library | |
| 3.3v Base I/O |
Memory Compilers (0.13μm: TS13SL — Mixed Signal CMOS)
| Library | Partner |
| RF-1P | |
| RF-2P | |
| SP SRAM | |
| SP SRAM | |
| DP SRAM | |
| Via ROM Generator | |
| Rad-hard Single Port SRAM | |
| Rad-hard Dual Port SRAM | |
| ASAP – 1PHD Small Bitcell | |
| ASAP – 1PRF | |
| ASAP – 2PHD | |
| ASAP – 2PRF | |
| STAR – 1PHD Small Bitcell | |
| STAR – 2PHD | |
| ASAP – VROM |
NVMs (0.13μm: TS13SL — Mixed Signal CMOS)
| Library | Partner |
| XPM Module (OTP Core), 16bit, 1Kb, 8Kb & 64Kb | |
| NVM SmartBit™ Technology |
Standard Cell Libraries (0.13μm: TS13SL — Mixed Signal CMOS)
| Library | Partner |
| Sage X2 – STD Cell Library | |
| SC7 Ultra High Den Library RVt | |
| SC7 Ultra High Den PMK RVt-HVt | |
| SC7 Ultra High Den Library HVt | |
| SC7 Ultra High Den PMK HVt | |
| Rad-hard Standard cell library | |
| ASAP – HD STD Cells | |
| ASAP – HS Metal Programmable STD Cells |
0.13μm: TS13LL — Low Leakage Mixed Signal CMOS
Analog IPs: Synopsys
I/O Libraries: Aragio Solutions and Synopsys
Memory Compilers: Synopsys
NVMs: Synopsys
Standard Cell Libraries: Synopsys
Analog IPs (0.13μm: TS13LL — Low Leakage Mixed Signal CMOS)
| Library | Partner |
| PLL 25-250MHz | |
| PLL 56.25-500MHz | |
| USB2.0 OTG UTMI + Level 3 PHY |
I/O Libraries (0.13μm: TS13LL — Low Leakage Mixed Signal CMOS)
| Library | Partner |
| ESD I/O Interface for High-speed USB OTG | |
| 3.3v Base I/O |
Memory Compilers(0.13μm: TS13LL — Low Leakage Mixed Signal CMOS)
| Library | Partner |
| ASAP – 1PRF | |
| ASAP – 2PRF | |
| ASAP – 1PHD Small Bitcell | |
| ASAP – 2PHD | |
| Single Port, High Density Contact/Via 23 ROM 1M Sync Compiler |
NVMs (0.13μm: TS13LL — Low Leakage Mixed Signal CMOS)
| Library | Partner |
| AEON/MTP Parallel |
STD Cells (0.13μm: TS13LL — Low Leakage Mixed Signal CMOS)
| Library | Partner |
| ASAP – HS Metal Programmable STD Cells | |
| ASAP – HD STD Cells |
0.13μm: CA13/SBL13 — Standard Logic, RF and SiGe
I/O Libraries: TowerJazz
Memory Compilers: Synopsys
NVMs: Novocell
Standard Cell Libraries: Synopsys and TowerJazz
I/O Libraries (0.13μm: CA13 / SBL13 — Standard Logic, RF and SiGe)
| Library | Partner |
| GPIO Inline Pad Library 3.3v/1.2v A13 | |
| GPIO Inline Pad Library 3.3v/1.5v A13 |
Memory Compilers (0.13μm: CA13 / SBL13 — Standard Logic, RF and SiGe)
| Library | Partner |
| Diffusion ROM | |
| Diffusion ROM HVt | |
| RF-1P/2P | |
| RF-1P/2P HVt | |
| DP SRAM HVt | |
| SP SRAM | |
| DP SRAM |
NVMs (0.13μm: CA13 / SBL13 — Standard Logic, RF and SiGe)
| Library | Partner |
| NVM SmartBit™ Technology |
Standard Cell Libraries (0.13μm: CA13 / SBL13 — Standard Logic, RF and SiGe)
| Library | Partner |
| HD STD Cell Library A13LP 1.2V | |
| HD STD Cell Library A13LP 1.2V HVt | |
| HD STD Cell Library A13LP 1.5V | |
| HD STD Cell Library A13LP 1.5V HVt | |
| STD Cell Library A13 1.2V | |
| STD Cell Library A13 1.2V HVt | |
| STD Cell Library A13 1.5V | |
| STD Cell Library A13 1.5V HVt |
0.18μm: TS18SL — Mixed Signal CMOS
Analog IPs: Arm, Chipus (NEW), Mixel, MOSCAD, Ramon Chips, Rio Systems (NEW), S3 Group and Synopsys
I/O Libraries: ARM, Ramon Chips, RedCat Devices and TowerJazz
Memory Compilers: ARM, Mentor Graphics (NEW), Ramon Chips, RedCat Devices (NEW), Synopsys and TowerJazz
NVMs: Kilopass, Novocell, Sidense, Synopsys and TowerJazz (NEW)
Processors: ARM and CEVA
RF IPs: SIEVA Networks
Standard Cell Libraries: ARM, Ramon Chips, RedCat Devices, Synopsys and TowerJazz
Analog IPs (0.18μm: TS18SL — Mixed Signal CMOS)
| Library | Partner |
| USB 1.1 for TS16 F1/B2 process | |
| NEW CM2012gf - Low-Power 8-bit SAR ADC | |
| NEW CM4015gf - 4MHz Ultra-Low-Power Oscillator | |
| NEW CM1015gf - 17.5nA Current Bias with Enable | |
| 80 Mbps to 1Gbps data rate MIPI Tranciever | |
| 4 Channel LVDS Serializer with 25MHz to 165MHz input clock | |
| LVDS TX up to 1.25 Gbps. | |
| MIPI slave compliant with 1.0 standard for D-PHY | |
| High performance PLL based frequency synthesizer. | |
| LVDS Transceiver up to 600 Mbps. | |
| MDDI T2 Client PHY compliant with VESA MDDI Client spec | |
| VGA with gain 0.5 to 128 | |
| 120mA 3.3V to 1.8V regulator | |
| 13 bits 2.56MS/s SAR ADC | |
| 10 bits 16MS/s current steering DAC | |
| Low-power bandgap | |
| Low-noise bandgap reference | |
| Line driver 0.5A | |
| Power-on reset circuit for 1.8V and 3.3V | |
| Rad-hard RS422 I/O buffers | |
| Rad-hard All-digital DLL library | |
| Rad-hardEmbedded capless voltage regulator, from 5V to 1.8-3.3V | |
| NEW RS5120 - Broadband variable gain amplifier | |
| NEW RS5130 - Broadband analog baseband | |
| NEW RS5200 - Programmable gain low noise amplifier | |
| NEW RS6310 - 6th order gmC low pass filter | |
| NEW RS6400 - 6th order switched capacitor filter | |
| NEW RS3020 - Integer-N PLL synthesizer | |
| NEW RS3120 - Sigma-delta fractional-n PLL synthesizer | |
| NEW RS8601 - 8-bit differential successive approximation ADC | |
| NEW RS8610 - 8-bit differential interleaved successive approximation ADC | |
| NEW RS8640 - 3-level quantizer | |
| NEW RS8641 - 2-bit ADC | |
| NEW RS8720 - RF power detector | |
| NEW RS8730 - RF power detector | |
| NEW RS8000 - SPI interface | |
| NEW RS8020 - SPI interface | |
| NEW RS8100 - 3rd order Mash 1-1-1 sigma delta modulator | |
| NEW RS8130 - 4th order delta sigma modulator | |
| 10 Bit 60 MSPS Pipeline ADC | |
| 10 Bit 30 MSPS Pipeline ADC | |
| Oscillator LP 32KHz | |
| PLL 50-250MHz | |
| Extended resolution Multi-Antenna WLAN baseband AFE (802.11abg) | |
| 16-bit, 9.6kHz Sampling Frequency, General Purpose Codec | |
| PLL 225-500MHz | |
| PLL 325-700MHz | |
| 20B Audio Stereo DAC 2pF Load | |
| 20B Audio Stereo DAC 40pF Load | |
| USB2.0 LS/FS (USB1.1 Transceiver) | |
| USB2.0 OTG UTMI + Level 3 PHY | |
| USB2.0 PHY | |
| BGAP 3V | |
| Capless LDO Voltage Regulator | |
| LDO Voltage Regulator |
I/O Libraries (0.18μm: TS18SL — Mixed Signal CMOS)
| Library | Partner |
| GPIO Inline I/O Pad Library | |
| GPIO Staggered I/O Pad Library | |
| Rad-hard I/O cell library | |
| Rad-hard LVDS library | |
| Rad-hard I/O (core 1.8V ext 3.3V) (RadPad18) | |
| Rad-hard I/O 3.3V only (RadPad33) | |
| PIO250 3.3v Super Compact Inline Pad Over Logic I/O | |
| PIO510 5V/1.8V Inline Pad Over Logic I/O | |
| IO510 5V/1.8V Inline I/O | |
| PIO150 1.8v Super Compact Inline Pad Over Logic I/O | |
| CIO150 1.8v Super Compact Inline I/O | |
| CIO250 3.3v Super Compact Inline I/O |
Memory Compilers (0.18μm: TS18SL — Mixed Signal CMOS)
| Library | Partner |
| RA1 Single-Port SRAM | |
| RA2 Dual-Port SRAM | |
| RF1 Single-Port Register File | |
| RF2 Two-Port Register File | |
| Via ROM Generator | |
| NEW Novelics coolSRAM – 1T embedded memory IP | |
| Rad-hard Single Port SRAM | |
| Rad-hard Dual Port SRAM | |
| Rad-hard SRAM 1kbit x1 (RC1KbitRHMx1) | |
| Rad-hard SRAM 2kbit x1 (RC2KbitRHMx1) | |
| Rad-hard SRAM 4kbit x1 (RC4KbitRHMx1) | |
| Rad-hard SRAM 8kbit x1 (RC8KbitRHMx1) | |
| Rad-hard SRAM 16kbit x1 (RC16KbitRHMx1) | |
| NEW Rad-hard SRAM 32kbit x1 (RC32KbitRHMx1) | |
| Rad-hard SRAM 64kbit x1 (RC64KbitRHMx1) | |
| ASAP – 1PHD | |
| ASAP – 2PHD | |
| ASAP – Dual-PortRegister File | |
| ASAP – VROM | |
| Single Port, High Density SRAM 4M Sync Compiler | |
| RS160 Single Port SRAM | |
| RD130 Dual Port SRAM | |
| RO160 Via ROM |
NVMs (0.18μm: TS18SL — Mixed Signal CMOS)
| Library | Partner |
| XPM Module (OTP Core) | |
| NVM SmartBit™ Technology | |
| ULP OTP Memory, 128bits-256Kbits | |
| SLP OTP Memory, 128bits-256Kbits | |
| NOVeA 2.0 | |
| YFlash 64b FTP for TS18SL 3.3V/1.8V process only | |
| NEW YFlash 16Kb OTP with Charge-Pump for TS16 F1/B2 process |
Processors (0.18μm: TS18SL — Mixed Signal CMOS)
| Library | Partner |
| ARM7TDMI - 32B RISC Processor | |
| ARM922T - 32B RISC Processor | |
| CEVA Teak 1.8v DSP Core | |
| CEVA Xpert-Teak 1.8v DSP Sub-System |
RF IPs (0.18μm: TS18SL — Mixed Signal CMOS)
| Library | Partner |
| LNA SN035 | |
| RF Mixer SN055 | |
| VCO SN040 |
Standard Cell Libraries (0.18μm: TS18SL — Mixed Signal CMOS)
| Library | Partner |
| Sage X - STD Cell Library | |
| Metro - STD Cell Library for TS18SL, TS16SL and TS152SL | |
| Rad-hard Standard cell library | |
| Rad-hard Standard Logic 1.8V (RadLib18) | |
| Rad-hard Standard Logic 3.3V (RadLib33) | |
| High Density Metal Programmable Logic Library Full | |
| FS310 STD cells | |
| FS120 STD Cells | |
| FS020 STD Cells 0.18um LV 0.9-2.2v Library | |
| FS510HDPM STD cells | |
| FS510HDSL STD cells |
0.18μm: TS18PM — Power Management
I/O Libraries: TowerJazz
Memory Compilers: ARM, Synopsys and TowerJazz
NVMs:
TowerJazz (NEW)
Processors: ARM and CEVA
Standard Cell Libraries: ARM, Synopsys and TowerJazz
I/O Libraries (0.18μm: TS18PM — Power Management)
| Library | Partner |
| PIO510 5V/1.8V Inline Pad Over Logic I/O | |
| IO510 5V/1.8V Inline I/O |
Memory Compilers (0.18μm: TS18PM — Power Management)
| Library | Partner |
| RA1 Single-Port SRAM | |
| RA2 Dual-Port SRAM | |
| RF1 Single-Port Register File | |
| RF2 Two-Port Register File | |
| Via ROM Generator | |
| ASAP – 1PHD | |
| ASAP – 2PHD | |
| ASAP – 2PRF | |
| ASAP – VROM | |
| Single Port, High Density SRAM 4M Sync Compiler, Tower 180G SVt | |
| RS160 Single Port SRAM | |
| RD130 Dual Port SRAM | |
| RO160 Via ROM |
NVMs (0.18μm: TS18PM — Power Management)
| Library | Partner |
| NEW YFlash 32b FTP for TS18PM 5V and 5V/1.8V process | |
| YFlash 64b FTP for TS18PM and TS18SL, 5V and 5V/1.8V processes | |
| YFlash 4Kb FTP with Charge-Pump for TS18PM 5V and 5V/1.8V process |
Processors (0.18μm: TS18PM — Power Management)
| Library | Partner |
| ARM7TDMI - 32B RISC Processor | |
| ARM922T - 32B RISC Processor | |
| CEVA Teak 1.8v DSP Core | |
| CEVA Xpert-Teak 1.8v DSP Sub-System |
Standard Cell Libraries (0.18μm: TS18PM — Power Management)
| Library | Partner |
| Sage X - STD Cell Library | |
| High Density Metal Programmable Logic Library Full, Tower 180SL SVt | |
| FS120 STD Cells | |
| FS020 STD Cells 0.18um LV 0.9-2.2v Library | |
| FS510HDPM STD cells | |
| FS510HDSL STD cells |
0.18μm: SBC18 — BiCMOS SiGe or Silicon Germanium
Analog IPs: ADSANTEC and Pacific MicroCHIP Corp.
RF IPs: TowerJazz
Analog IPs (0.18μm: SBC18 — BiCMOS SiGe or Silicon Germanium)
| Library | Partner |
| Reconfigurable 1:16/1:8 Deserializer [ASNT2012] | |
| Reconfigurable 16:1/8:1 Serializer [ASNT1011] | |
| 1Gbps LVDS/CMOS Converter [ASNT3010] | |
| 35GHz Output Driver [PMCC-OBUF35G] | |
| 50GHz Programmable Divider [PMCC-DIV50G1] | |
| 30GHz Mixer [PMCC-IRMIX30G] | |
| 20-30GHz VCO [PMCC-VCO24] |
RF IPs (0.18μm: SBC18 — BiCMOS SiGe or Silicon Germanium)
| Library | Partner |
| Quad-Current Charge Pump [JZ15X74CP] | |
| LNA + Mixer Front-End [JZ1C030] | |
| RSSI [JZ1DE30] | |
| 5.2GHz LNA [JAZ10100] | |
| IQ Modulator [JZ1EF30] | |
| AGC [JZ1EF30] | |
| Up-Converter [JZ1EF30] |
0.18µm: CA18/SBC18 — Standard Logic/RF/SiGe
Analog IPs: Rio Systems (NEW), SaberTek, Tahoe RF Semiconductor and IQ Analog (NEW)
I/O Libraries: Conexant
Memory Libraries: ARM
NVMs: Novocell and TowerJazz
RF IPs: SaberTek and Tahoe RF Semiconductor
Standard Cell Libraries: ARM and Conexant
Analog IPs (0.18μm: CA18 / SBC18 — Standard Logic/RF/SiGe)
| Library | Partner |
| NEW RS6120 - 6th order RC complex filter | |
| NEW RS6300 - 2nd order gmC complex filter | |
| NEW RS3000 - Integer-N PLL synthesizer | |
| NEW RS8620 - 16-bit sigma-delta ADC | |
| NEW RS8700 - RF power detector | |
| NEW RS8710 - RF power detector | |
| NEW RS8010 - SPI interface | |
| NEW RS8030 - SPI interface | |
| NEW RS8110 - 3rd order Mash 1-1-1 sigma delta modulator | |
| NEW RS8120 - 4th order delta sigma modulator | |
| NEW RS6100 - 2nd order RC complex filter | |
| NEW RS6110 - 4th order RC complex filter | |
| NEW RS3110 - Sigma-delta fractional-n PLL synthesizer | |
| NEW RS4400 - Complex modulator | |
| NEW RS4410 - IQ modulator | |
| NEW RS5110 - Dual channel digitally controlled linear-dB variable gain amplifier | |
| NEW RS3100 - Sigma-delta fractional-n PLL synthesizer | |
| NEW RS4420 - IQ demodulator | |
| NEW RS4700 - Broadband RF switching matrix | |
| NEW RS4800 - RF phase compensator | |
| NEW RS7100 - Broadband receiver front-end | |
| NEW RS7200 - Broadband transmitter front-end | |
| NEW RS8510 - 8-bit R-2R single ended digital to analogue converter | |
| NEW RS8511 - 8-bit R-2R differential digital to analogue converter | |
| NEW RS8600 - 8-bit single ended successive approximation ADC | |
| NEW RS3010 - Integer-N PLL synthesizer | |
| NEW RS4300 - 4-bit DC-2GHz digital attenuator | |
| NEW RS4301 - Dual channel 4-bit DC-2GHz digital attenuator | |
| PGA, 1~900MHz (SBR_PGA_30dB_900_JSG18_2) | |
| RC calibration, 40MHz (SBR_RCCAL_JSG18_1) | |
| Bandgap + Iref (SBR_BG_JSG35_1) | |
| LPF, DC to 0.75~14MHz (SBR_LPF_7P2Z_14M_JSG18_1) | |
| LPF, 1~900MHz (SBR_LPF_900M_JSG18_1) | |
| LPF, 1~900MHz (SBR_LPF_900M_JSG18_2) | |
| PGA, DC~40MHz (SBR_PGA_40dB_40_JSG18_1) | |
| PGA, 1~900MHz (SBR_PGA_30dB_900_JSG18_1) | |
| Bandgap + Iref (SBR_BG_JSG18_1) | |
| Bandgap + Iref (SBR_BG_JSG18_2) | |
| LDO (SBR_LDO_40m_JSC18_1) | |
| Receiver IF VGA [TRFS-158jz] | |
| GPS Receiver [TRFS-159jz] | |
| Mixer (L1 & L2) [TRFS-103jz] | VCO [TRFS-205jz] |
| NEW Dual 12-bit 64-Msps Analog-to-Digital Converter (ADC_GTO_64MJ18) | |
| NEW Dual 12-bit 200-Msps Digital-to-Analog Converter (DAC_GTO_200M33VJ18) | |
I/O Libraries (0.18μm: CA18/SBC18 — Standard Logic/RF/SiGe)
| Library | Partner |
| GPIO Inline Pad Library 5.0v-only | |
| GPIO Inline Pad Library 3.3v/1.8v | |
| GPIO Inline Pad Library 3.3v-only |
Memory Compilers (0.18μm: CA18/SBC18 — Standard Logic/RF/SiGe)
| Library | Partner |
| RA1 Single-Port SRAM | |
| RA2 Dual-Port SRAM | |
| RF1 Single-Port Register File | |
| RF2 Two-Port Register File | |
| ROD Diffusion ROM |
NVMs (0.18μm: CA18/SBC18 — Standard Logic/RF/SiGe)
| Library | Partner |
| NVM SmartBit™ Technology | |
| 3v, 350mA fuse |
RF IPs (0.18μm: CA18/SBC18 — Standard Logic/RF/SiGe)
| Library | Partner |
| PGA, 1~900GHz (SBR_PGA_30dB_900_JSG18_1) | |
| Complete RX, 57~67GHz (SBR_RX_60G_JSG18_1) | |
| LNA+Detector, 75~105GHz (SBR_RX_94G_JSG18_1) | |
| PA, 57~67GHz (SBR_PA_60G_JSG18_1) | |
| LNA, 0.6~3GHz (SBR_LNA_WB_JSC18_1) | |
| RXMIX,TIA, 0.7~3GHz (SBR_RXMX_2G_JSG18_1) | |
| LNA,MIX,TIA, 0.7~3GHz (SBR_RXFE_WB_JSC18_1) | |
| PFD + CP, 0.01~0.04GHz (SBR_PFDCP_40M_JSC18_1) | |
| Xtal buffer, 0.01~0.04GHz (SBR_XTLBUF_40M_JSG18_1) | |
| Xtal buffer, 0.01~0.04GHz (SBR_XTLBUF_40M_JSG18_2) | |
| Sigma-Delta mod, 0.04GHz (SBR_SIGMADEL_40M_JSC18_1) | |
| Programmable frequency divider, 2GHz (SBR_FDIV_2G_JSG18_1) | |
| Programmable frequency divider, 8GHz (SBR_FDIV_8G_JSG18_1) | |
| PFD + CP, 0.01~0.04GHz (SBR_PFDCP_40M_JSC18_1) | |
| Xtal buffer, 0.01~0.04GHz (SBR_XTLBUF_40M_JSG18_1) | |
| Complete SX, 40GHz (SBR_SX_40G_JSG18_1) | |
| VCO, 5.5~7GHz (SBR_VCO_6G_JSC18_1) | |
| PFD + CP, 0.01~0.04GHz (SBR_PFDCP_40M_JSC18_1) | |
| LNA, 23~29GHz (SBR_LNA_24G_JSG18_1) | |
| LNA, 77~82GHz (SBR_LNA_77G_JSG18_1) | |
| LNA, 75~105GHz (SBR_LNA_94G_JSG18_1) | |
| LNA, 75~105GHz (SBR_LNA_94G_JSG18_2) | |
| LNA, 57~67GHz (SBR_LNA_60G_JSG18_1) | |
| LPF, 1~900GHz (SBR_LPF_900M_JSG18_1) | |
| PA, 57~67GHz (SBR_PA_60G_JSG18_2) | |
| PA, 21~27GHz (SBR_PA_24G_JSG18_1) | |
| PA, 75~80GHz (SBR_PA_77G_JSG18_1) | |
| TXMIX, 57~67GHz (SBR_TXMX_60G_JSG18_1) | |
| Complete TX, 57~67GHz (SBR_TX_60G_JSG18_1) | |
| RXMIX, 57~66GHz (SBR_RXMX_60G_JSG18_1) | |
| RXMIX, 23~29GHz (SBR_RXMX_24G_JSG18_1) | |
| RXMIX, 77~82GHz (SBR_RXMX_77G_JSG18_1) | |
| RXFE,LPF,PGA, 0.7~3GHz (SBR_RX_2G_JSC18_1) | |
| PA, 0.7~1GHz (SBR_PA_900M_JSC18_1) | |
| PA, 1.7~2.6GHz (SBR_PA_2G_JSC18_1) | |
| PA, 0.7~3GHz (SBR_PA_WB_JSC18_1) | |
| VCO, 40GHz (SBR_VCO_40G_JSG18_1) | |
| Programmale Frequency Divider, 40GHz (SBR_FDIV_40G_JSG18_1) | |
| 2-9GHz VCO [TRFS-206-15jz] | |
| Sigma Delta Modulator [TRFS-261jz] | |
| Charge Pump [TRFS-265jz] | |
| Phase-Frequency Detector [TRFS-264jz] | |
| Ref Divider [TRFS-263jz] | |
| RF Divider [TRFS-262jz] |
Standard Cell Libraries (0.18μm: CA18/SBC18 — Standard Logic/RF/SiGe)
| Library | Partner |
| Sage X - STD Cell Library | |
| Metro - STD Cell Library | |
| STD Cell Library 3.3v | |
| STD Cell Library 5.0v |
0.25µm: CA25 — Digital CMOS, Analog/Mixed Signal, High Voltage and RF
I/O Library: TowerJazz
Standard Cell Libraries: TowerJazz
I/O Library (0.25µm: CA25 — Digital CMOS, Analog/Mixed Signal, High Voltage and RF)
| Library | Partner |
| GPIO Inline Pad Library 3.3v-only |
Standard Cell Libraries (0.25µm: CA25 — Digital CMOS, Analog/Mixed Signal, High Voltage and RF)
| Library | Partner |
| STD Cell Library 3.3v |
0.25µm: CP05, BCD25 — 5V Digital and Mixed Signal, RF Power and High Voltage CMOS
I/O Libraries: TowerJazz
NVM: TowerJazz
Standard Cell Libraries:
Nangate and TowerJazz
I/O Libraries (5Vm: CP05, BCD25 — 5V Digital and Mixed Signal, RF Power and High Voltage CMOS)
| Library | Partner |
| GPIO Inline Pad Library 5.0v-only | |
| GPIO Inline Pad Library 3.3v/2.5v |
NVM (5Vm: CP05, BCD25 — 5V Digital and Mixed Signal, RF Power and High Voltage CMOS)
| Library | Partner |
| GPIO Inline Pad Library 3.3v/2.5v |
Standard Cell Libraries (5Vm: CP05, BCD25 — 5V Digital and Mixed Signal, RF Power and High Voltage CMOS)
| Library | Partner |
| HD STD Cell Library 5.0v | |
| STD Cell Library 5.0v | |
| STD Cell Library |
0.35μm: SBC35 — BiCMOS SiGe or Silicon Germanium
Analog IPs: TowerJazz
I/O Library: TowerJazz
NVM: TowerJazz
RF IPs: TowerJazz
Standard Cell Library: TowerJazz
Analog IPs (0.35μm: SBC35 — BiCMOS SiGe or Silicon Germanium)
| Library | Partner |
| Bandgap 1.195V [JZ20160] | |
| Power-On Reset [JZ21280] |
I/O Library (0.35μm: SBC35 — BiCMOS SiGe or Silicon Germanium)
| Library | Partner |
| GPIO Inline Pad Library 3.3v-only |
NVM (0.35μm: SBC35 — BiCMOS SiGe or Silicon Germanium)
| Library | Partner |
| 7v, 350mA fuse |
RF IPs (0.35μm: SBC35 — BiCMOS SiGe or Silicon Germanium)
| Library | Partner |
| LNA + Mixer [JAZ1CEA0] | |
| 600MHz Prescaler [JZ25F80PRS] | |
| Phase-Frequency Detector [JZ15F80PD] | |
| IF Mixer [JZ1FE70] | |
| Charge Pump [JZ15X70CP] | |
| 2.7GHz Prescaler [JZ15F80PRS] | |
| Up-Converter [JZ19E70] | |
| PA Driver [JZ1DE70] | |
| Automatic Power Control (APC) [JZ19E70] | |
| IQ Modulator [JZ19E70] | |
| Limiter/RSSI [JZ1GE70] | |
| 1.9GHz LNA [JZ10E70] |
Standard Cell Library (0.35μm: SBC35 — BiCMOS SiGe or Silicon Germanium)
| Library | Partner |
| STD Cell Library |
0.5µm: C05 — 5V Digital and Mixed Signal
I/O Library: TowerJazz
Standard Cell Library: TowerJazz
I/O Library (0.5μm: C05 — 5V Digital and Mixed Signal)
| Library | Partner |
| GPIO Inline Pad Library 5.0v-only |
Standard Cell Library (0.5μm: C05 — 5V Digital and Mixed Signal)
| Library | Partner |
| STD Cell Library |




